1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to integrated circuits implementing vertical transistors having annular gate structures.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Semiconductor memory devices, such as dynamic random access memory (DRAM) devices, are widely used for storing data in systems such as computer systems. A DRAM memory cell typically includes an access device such as a field effect transistor (FET) coupled to a storage device such as a capacitor. The access device allows the transfer of charges to and from the storage capacitor thereby facilitating read and write operations in the memory device. The memory cells are typically arranged in a number of rows and columns to provide a memory array.
With the constantly increasing demand for higher data storage capacity, memory arrays are becoming more dense. Memory density is typically limited by current processing technologies used for fabrication of the memory arrays. One technique for providing higher density memory arrays is to incorporate vertical technology in fabricating the access transistors. Among the concerns in fabricating memory devices is to provide memory cells with minimal leakage to prevent the loss of storage cell data. Further, alpha-particle induced soft errors which alter the data stored in the memory cells should also be considered, and simplification in fabrication techniques may also be desirable.